Which TWO of the following accurately describe constraints on the location of the Tightly Coupled Memory (TCM) regions in a Cortex-R4 processor? (Choose two)
In a Cortex-A9 MPCore cluster with four processors, which of the processors can be interrupted by a software-generated interrupt?
Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?
In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?
Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?
Before execution:
R0=0xFFFFFFFF
R1 = ?
EOR R0, R0, R1
If R0=0x00000000 after executing the EOR instruction above, what was the value in R1 before the instruction executed?
In which of these cases would code have better performance when compiled for Thumb state than when compiled for ARM state?
To ensure optimum efficiency when programming in C, what is the recommended maximum number of arguments to be passed to a function?
In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)
In an ARMv7-A processor that includes the Advanced SIMD extension (NEON), where are the data values operated on by NEON instructions stored?
When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?
Which of the following is an advantage of the single-step debug technique?
In general, when programming in C, stack accesses will be reduced by:
Which of the following is an optional extension to the ARMv7-A architecture?
If the processor is in User mode and then an IRQ interrupt occurs:
If the performance of an application remains unchanged when the core clock speed of a Cortex-A9 processor is reduced, what can you deduce about the system?
In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)
Capturing processor execution trace is characterized as being:
Assume a little-endian system.
What is the value of R5 after the execution of the following piece of code?
A simple system comprises of the following memory map:
Flash - 0x0 to 0x7FFF
RAM - 0x10000 to 0X17FFF
When conforming to the ABI, which of the following is a suitable initial value for the stack pointer?
When using the default ARM tool-chain libraries for bare-metal applications. I/O functionality is rerouted and handled by a connected debugger. This is often referred to as semihosting. Which one of the following explanations BEST describes how this feature can be implemented by a debugger?
What is the value of r0 after executing the following instruction sequence?
MOV r0, #200
MOV r5, #1
STR r3, [r0, r5, LSL#3]!
Which of the following is a REQUIRED feature in the ARMv7 architecture?
The automatic removal of a cache line from a cache to free the location is known as cache line:
Clicking the Start button in a debugger:
An embedded application running on an ARM processor is not meeting its expected performance target. The target hardware on which the application is running allows the frequency of the CPU to be increased independently from the memory system.
The CPU frequency is increased from 800 MHz to 1 GHz and experiments verify that the application performance does not increase.
Which one of the following statements MUST BE TRUE?
Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:
What architecture does the ARM11 MPCore implement?
It is common to declare structures as "packed" in order to minimize data memory size. Which of the following accurately describes the effect of this?
Optimizing for space will:
On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?