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ARM EN0-001 ARM Accredited Engineer Exam Practice Test

Demo: 31 questions
Total 210 questions

ARM Accredited Engineer Questions and Answers

Question 1

The following C function is compiled with hard floating point linkage.

float function(int a, float b, int c, float d);

Which register is used to pass argument c?

Options:

A.

R0

B.

R1

C.

R2

D.

R3

Question 2

During an investigation into a software performance problem an engineer doubles the clock frequency of a cached ARM processor running the software. Unfortunately the performance of the application does not increase by very much, despite running on the processor for 100% of the time. What is likely to be the main bottleneck in the system?

Options:

A.

The processor is context switching between multiple processes

B.

Performance is limited by the speed of external memory

C.

The processor is taking too long to execute branch instructions

D.

The system is raising interrupts too fast for the processor to handle them

Question 3

When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?

Options:

A.

Writes dirty data cache lines to memory

B.

Reloads dirty data cache lines from memory

C.

Speculatively preloads data into the cache

D.

Writes dirty data cache lines to memory and marks those lines as invalid

Question 4

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

Options:

A.

Instruction cache clean only

B.

Instruction cache invalidate only

C.

Data cache clean and instruction cache invalidate

D.

Data cache invalidate and instruction cache invalidate

Question 5

Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.

LDR r0, [r1]

STR r0, [r2]

STR r3, [r3]

R1 points to a location in normal memory. R2 and R3 point to device memory.

Which of the following statements best describes the ordering rules which apply to this sequence?

Options:

A.

The two writes to device memory will happen in program order, but the read can be performed out of order

B.

The memory accesses can happen in any order

C.

The memory accesses will happen in program order

D.

The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

Question 6

The purpose of a translation lookaside buffer (TLB) is to:

Options:

A.

Protect memory.

B.

Improve performance.

C.

Implement virtual memory,

D.

Ensure correct ordering of memory operations.

Question 7

A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:

The second CPU receives the message using the instructions:

On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?

Options:

A.

A only

B.

C only

C.

B and C

D.

A and D

Question 8

Using a lower optimization level when compiling will:

Options:

A.

Produce faster code.

B.

Produce smaller code.

C.

Produce non standard-compliant code.

D.

Produce code that might be easier to debug.

Question 9

In Architecture ARMv7-A which one of the following has a known physical address at power-on reset?

Options:

A.

The exception vector table

B.

The Memory Management Unit (MMU) translation table

C.

The Stack Pointer (SP)

D.

The System Control Register (SCTLR)

Question 10

As part of the ABI specification, the AAPCS defines which of the following?

Options:

A.

How many levels of nested function calls are permitted on ARM systems

B.

How to measure the maximum amount of stack required by an application

C.

On which mode's stack you need to save the return address in a non-leaf function

D.

Which registers need to be preserved by a function

Question 11

Which of the following would enable the use of a symmetric multiprocessing (SMP) operating system?

Options:

A.

A dual-core Cortex-A9 processor

B.

A Cortex-R4 processor with a Cortex-M3 system controller

C.

A Cortex-A8 processor with a graphics processing unit (GPU)

D.

A uni-core Cortex-A5 processor with a digital signal processor (DSP)

Question 12

If a Generic Interrupt Controller (GIC) implements 64 priority levels, which priority field bits hold the priority value?

Options:

A.

bits [5:0]

B.

bits [7:2]

C.

bits [15:10]

D.

bits [31:26]

Question 13

When using the ARM Compiler (armcc), which of the following possible keywords can be used to remove padding bytes from a structure?

Options:

A.

__package

B.

__packed

C.

__compact

D.

__compress

Question 14

Which of the following instructions can be used to enter a power saving mode?

Options:

A.

PLD

B.

PLI

C.

WFE

D.

DSB

Question 15

What view in a debugger displays the order in which functions were called?

Options:

A.

The Call Stack view

B.

The Memory view

C.

The Registers view

D.

The Variables view

Question 16

Which of the following is TRUE for dynamically linked executables?

Options:

A.

They can contain unresolved relocations

B.

They contain the code and data for all libraries they use

C.

They are larger than an equivalent statically linked application

D.

They are designed to be run standalone with no other supporting software

Question 17

In an ARMv7-A system, the following C function calculates a simple checksum for an input data packet of variable length. The checksum is defined to be the sum of all of the 16-bit data items in the packet modulo 65536. The parameter data_items contains the number of 2-byte data items in the packet, and it cannot be zero by design.

When using an ARM compiler, which TWO of the following optimizations could improve the performance of this code? (Choose two)

Options:

A.

Use a do/while loop instead of a for loop

B.

Change the type of sum to be an unsigned short

C.

Change the type of i to be an unsigned int

D.

Use signed variables instead of unsigned variables

E.

Declare sum as a global variable

Question 18

In the Generic Interrupt Controller (GIC) architecture, which of the following ID numbers are reserved for interrupts that are private to a CPU interface?

Options:

A.

ID0-ID7

B.

ID0-ID15

C.

ID0-ID31

D.

ID0-ID63

Question 19

Which one of the following statements is TRUE for software breakpoints?

Options:

A.

Limited software breakpoints can be placed in code running from ROM

B.

Each software breakpoint requires one watchpoint resource in the debug hardware

C.

Each software breakpoint requires one breakpoint resource in the debug hardware

D.

The number of available software breakpoints is not limited by the debug hardware

Question 20

A function written in C has the prototype:

void my_function(float a. double b, float c);

The function is built and linked into an application using hard floating-point linkage. What registers are used to pass arguments to the function?

Options:

A.

a->s0; b->d0; c->s1

B.

a->s0; b->d1; c->s1

C.

a->d0; b->d1; c->d2

D.

a->s0; b->d1; c-> s2

Question 21

An Advanced SIMD intrinsic has the prototype:

int16x4_t vmul_n_s16(int16x4_t a, int16_t b);

How many multiplications does this intrinsic compute?

Options:

A.

1 multiplication

B.

4 multiplications

C.

16 multiplications

D.

64 multiplications

Question 22

Which ARMv7 instructions are recommended to implement a semaphore?

Options:

A.

SWP, SWPB

B.

TEQ, TST

C.

STC, SBC

D.

LDREX, STREX

Question 23

In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?

Options:

A.

D0..D31 and S0..S31 are separate register banks

B.

D0..D31 overlap with S0..S63

C.

D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers

D.

D0 overlaps with S0, D1 with S1 etc. up to D31 and S31

Question 24

When using the Performance Monitoring Unit to count runtime events the counter registers are limited to 32-bits. How can more than 2A32 events be counted without significantly impacting the software performance?

Options:

A.

Register an interrupt which is triggered when the counter overflows

B.

Count the events using a 64-bit VFP register

C.

Allow one event type to use concatenated counter registers

D.

Poll the event counter, resetting it when the counter is close to overflowing

Question 25

Which THREE of the following items should be preserved by software when entering dormant mode? (Choose three)

Options:

A.

Current Program Status Register (CPSR)

B.

Contents of the Level 2 data cache

C.

The Floating Point Status and Control Register (FPSCR)

D.

All User mode general-purpose registers

E.

The CP15 Multiprocessor Affinity Register

F.

Contents of the Level 1 data cache

Question 26

Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?

Options:

A.

Cortex-M0+

B.

Cortex-M4

C.

Cortex-R4

D.

Cortex-A15

Question 27

Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?

Options:

A.

A dedicated real-time clock to provide the total cycle count

B.

Use of the divide-by 64 counting option to avoid an overflow of the cycle counter

C.

Use of the overflow interrupts, to extend the range of the built-in 32-bit counter

D.

Modification of the application software being profiled, to insert timestamps at regular intervals

Question 28

According to the EABI. what would the C size of () operator return when given the following structure?

Options:

A.

19

B.

20

C.

24

D.

28

Question 29

In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being handled, it is in which of the following states?

Options:

A.

Inactive

B.

Active

C.

Pending

D.

Edge-triggered

Question 30

In which of the following scenarios would cache maintenance operations be necessary in an ARMv7 system?

Options:

A.

Before executing code that uses the NEON instruction set

B.

Before handling an interrupt request raised by an external device

C.

Before checking the status of a semaphore

D.

Before reading cacheable memory that has been written to by an external bus master

Question 31

Which of these C99 keywords can be used to indicate that two arrays do not overlap?

Options:

A.

"pure"

B.

"volatile"

C.

"static"

D.

"restrict"

Demo: 31 questions
Total 210 questions